1. Field of the Invention
The present invention relates to a technology for filling a via hole that is formed in a semiconductor chip configured with an integrated circuit that includes a semiconductor chip having a stacked structure by using a conductor to electrically connect the upper and lower semiconductor chips to each other with a conductor. More particularly, the present invention relates to a technology for reducing a size of a via hole and filling the via hole with a desirable conductor by using a predetermined method, which is capable of being applied to the fine via hole that has a good conductivity.
2. Description of the Related Art
Since a function of integrated circuit has become more various, the configuration of the integrated circuit has been making rapid progress at a system level. Accordingly, stacking of chips that are made of various materials with various functions in three dimensions is on the rise as an important issue.
In order to stack the chips in three dimensions, it is necessary to vertically form the via holes through the chips and connect them with a conductor. The depth is generally several tens μm, and the diameter of the hole is reduced from several tens μm to several μm. In the process for forming the via hole, filling the narrow and deep via hole with desirable conductor is desperately needed and a difficult technology.